1. Technical Field of the Invention
The present invention relates to a method for programming memory cells of the Flash type.
The invention also relates to an architecture for programming memory cells, in particular of the Flash type.
The invention particularly, but not exclusively, relates to a memory device of the Flash type suitable for being used in compact disk (CD) players, video cameras, cell phones, and the like, and the following description is made with reference to this field of application for simplifying its illustration only.
2. Description of Related Art
As it is well known, Flash memories are non volatile memories, able to maintain the information also in the absence of power supply and organized so as to be erasable by sector.
The information contained in a common Flash memory cell is of the binary type, a first high logic value or bit ‘1’ corresponding to one erased state and a second low logic value or bit ‘0’ identifying a programmed state.
The programming operation can be conducted with a parallelism of 16 bits (according to the so called word mode) or 64 bits (according to the so called page mode), while the erasing operation generally always relates to an entire sector of the memory, whose current density varies from 0.5 to 2 MBits. These operations are managed by a microcontroller embedded in the Flash memory device that executes suitable programming and erasing algorithms contained in a ROM memory, in turn included in the Flash memory device.
The erasing time (like the programming time) should meet a specification that, in current memories, is of about 0.7 sec and that, in the future, will tend to decrease due to the increase of the speed of the applications whereon the same will be employed, such as for example in the use inside CD players, video cameras and cell phones, etc.
FIG. 1 shows the typical current-voltage [I-V] characteristics of two memory cells of the Flash type, respectively in the erased state (bit 1)-curve A, and in the programmed state (bit 0)-curve B. As it can be noted in such figure, the I-V characteristics increase starting from a minimum voltage value, respectively VTHEV for an erased cell and VTHPV for a programmed cell.
It is also known that an erasing operation of a Flash memory comprises three distinct steps: a pre-programming step (or ALL0); a real erasing step (or ERASE); and a soft-programming step (or SOFTP).
The ALL0 step comprises the pre-programming of an entire sector of the Flash memory to be erased so that all the Flash cells of this sector are under the same initial conditions as regards their threshold voltage value. This pre-programming of the cells of the sector usually occurs with a parallelism of 16 bits (per word).
The ERASE step comprises the erasing of the entire sector and its resolution thus depends on the density of the sector itself. This resolution is substantially the minimum memory portion that can be erased, which has dimensions ranging from 0.5 Mbits to 2 Mbits in the considered applications.
The SOFT Programming step has the aim of recovering those cells whose threshold voltage, at the end of the ERASE step, is lower than a minimum voltage value of the distribution of the erased cells (indicated with VTHDV). This SOFT Programming step has a typical parallelism of 16 bits.
The distributions of the threshold voltages of the cells of a sector of a Flash memory subjected to an erasing operation—after each one of the above-indicated steps—are shown in FIG. 2, respectively indicated with DALL0, DERASE and DSOFTP. The area C of the distribution DSOFTP graphically shows the portion of Flash cells whose threshold voltage is lower than the minimum voltage value VTHDV and that should thus undergo soft-programming.
The continuous scaling of the technological processes, with the consequent reduction of the dimension of the single Flash cells, has implied an increase of the unhomogeneity between the cells of a sector, for example between a cell on board and a cell in the center, causing a higher and higher spread in the distribution of the threshold voltages of the erased bits as highlighted in FIG. 3, the arrow F indicating a technological scaling from 0.35 um to 0.09 um.
FIG. 3 highlights how this spread has a direct impact on the need of soft-programming a distribution, having passed from distributions which did not need any soft-programming (like the distribution D corresponding to the case of the technology with 0.35 um) to distributions which are to be almost totally soft-programmed (like the distribution E corresponding to the case of the most recent technology with 0.09 um).
For the distributions of the most recent technologies, moreover, the Flash cells whose threshold voltage is distant from the minimum value VTHDV being numerous, the same need soft-programming ramps with final voltage differences .DELTA.V much higher than those of less recent technologies, reaching almost 5V in the case of the technologies with 0.09 um.
These two limitations make the soft-programming step, having much lower parallelism than that of the ERASE step, represent about 70% of the total erase time and thus it should be calibrated with care for respecting the specifications requested for a given Flash memory.
In particular, the erase time Terase is given by the sum of the times of the ALL0 (TALL0), ERASE (TERASE) and SOFT Programming (TSOFTP) steps:Terase=Σ(TALL0,TERASE,TSOFTP)
As already hinted at, the duration TALL0 of the ALL0 step depends on the density of the sector of the Flash memory to be erased, on the duration of the programming and on the adopted parallelism, i.e. on the number of bits that will be simultaneously programmed (16 bits in the word mode, 64 bits in the page mode).
For example, considering a sector with density equal to 0.5 Mbit, a duration of the programming equal to 5 usec and a parallelism of 16 bits, the duration of the ALL0 step will be:
                              T                      ALL            ⁢                                                  ⁢            0                          =                ⁢                              (                          density              ⁢                              /                            ⁢              parallelism                        )                    *          duration          ⁢                                          ⁢          programming                                        =                ⁢                                                            (                                  500000                  /                  16                                )                            *              5              *              10              ⁢                              ⅇ                                  -                  6                                                      ∼                    =                      160            ⁢                                                  ⁢            ms                              
The duration of the ERASE step instead depends on the duration of the erase pulse, on the overall voltage difference .DELTA.V to be applied and on the value of the single step of voltage (step_voltage) and it is thus equal to:TERASE=duration_erase_pulse*(ΔV/step_voltage)
Considering, for example, an erase pulse of duration 3 msec, an overall voltage difference ΔV of 5V and a value of the single step of voltage (step_voltage) of 125 mV it results:TEASE=3*10e−3(5/0.125)=120 msec
Finally, the duration of the SOFT Programming step depends, as in the case of the ALL0 step, on the density of the sector, on the duration of the programming, on the parallelism adopted and, finally, on the steps of voltage which allow to realize a programming ramp with a predetermined final voltage difference ΔV.
For example, if also in this case a sector of density equal to 0.5 Mbit, a programming duration equal to 5 usec, a parallelism of 16 bits, a final voltage difference ΔV of 3V with steps of 375 mV are considered, the duration of the SOFTP step will be:TSOFTP=(density/parallelism)*programming duration*(ΔV/step_voltage)=(500000/16)*5*10e−6*(3/0.375)=1250 msec
Therefore, the overall time of the erase step, in the above indicated hypotheses, will be equal to:Terase=Σ(TALL0,TERASE,TSOFTP)˜=160 msec+120 msec+1250 msec˜=1.5 sec
Time which, as it is easy to be verified, is widely out of the specifications of several applications.
Moreover, it is immediate to verify that the duration of the SOFT Programming step has a predominant impact on the total erase time, equal to about 70% as indicated above.
Also in the case in which the parallelism adopted were of 64 bits there would result:TALL0=(500000/64)*5*10e−6˜=40 msecTERASE=120 msec(does not depend on the adopted parallelism)TSOFTP=(500000/64)*5*10e−6*(3/0.375)˜=320 msec
The overall time of the erase step in this scenario would be thus equal to:Terase=Σ(TALL0,TERASE,TSOFTP)˜=40 msec+120 msec+320 msec˜=500 msec
It is thus evident that the reduction of the erase time is obtained by adopting a high parallelism and that therefore the reduction of the soft-programming time (which, as above said, represents 70% of the total erase time) is only a problem of parallelism.
The known erase methods thus provide, already in the design phase, a high parallelism of the soft-programming step. In this case, the soft-programming architecture associated with the Flash memory must necessarily comprise a charge pump designed for supplying the Flash cells with programming currents taking into consideration the “worst case”, i.e., that in which the soft-programming step occurs with the maximum parallelism, the current to be supplied growing with the parallelism.
For example, if a Flash cell absorbs, during the soft-programming step, a current Icell, the charge pump will have to supply a current value Icharge_pump given by the following relation:Icharge_pump=Icell*parallelism
Taking then into consideration a value of this current Icell equal to about 100 uA, the current that the charge pump must supply depends on the parallelism and it is equal to:parallelism 16 bits:Icharge_pump=100 uA*16 bit=1.6 mAparallelism 32 bits:Icharge_pump=100 uA*32 bit=3.2 mAparallelism 64 bits:Icharge_pump=100 uA*64 bit=6.4 mA
The most evident disadvantages of this approach result in a growing occupation in terms of silicon area by the charge pump when the chosen parallelism grows and a worse tracking on the process, since technologically more mature processes and thus Flash cells being less and less demanding in terms of current would no more justify the design choices aimed at increasing the maximum current which can be supplied by the charge pump.
If, in the example of parallelism 64 bits, the current Icell absorbed by the cell decreased from 100 uA to 60 uA it would be enough to have:Icharge_pump=60 uA*64 bit=3.8 mA
This value is considerably lower than 6.4 mA which was the design target for the charge pump of the soft-programming architecture based on the known method. This, therefore, is over-dimensioned with consequent waste of resources.